The continuous development of integrated circuit (IC) technology has brought about a trend in electronics toward miniaturization, intelligence, high performance and high reliability. Packaging is critical not only to the performance of individual ICs but to whether the ICs can constitute a compact, low-cost, reliable electronic system. As IC dies continue shrinking in size and increasing in integration, more and more stringent requirements are being placed on IC packaging.
As shown in FIG. 1, fan-out wafer-level packaging (FOWLP) is a packaging technique to rearrange individual dies 2 diced from a wafer on a new carrier 1 for wafer-level packaging. New packages 3 can then be formed on the new carrier 1 using conventional wafer-level packaging techniques (FIG. 2). FIG. 4 depicts a schematic illustration of a single one of the packages. As shown in FIG. 4, the die 2 is embedded in the package 3, and the package 3 further includes solder pads 4 for the die 2 and a rewiring structure which is composed of a lower insulating layer 7, a metal layer 5 and an upper insulating layer 6 and fabricated by processes including photolithography, CVD, PVD, etching and electroplating. Moreover, solder balls 8 at new I/O ports (i.e., electrical connection terminals leading from the metal layer 5) are uniformly distributed on the new package 3. The multiple new packages 3 are arranged on the new carrier 1, forming the structure shown in FIG. 2.
A typical rewiring process in the FOWLP technique includes lithographically defining shapes and positions of the upper insulating layer 6, the metal layer 5 and the lower insulating layer 7 and then forming the insulating layers and the metal layer using CVD, PVD, electroplating and other processes. A mainstay (i.e., mask-based) photolithography process defines the shapes and positions usually by shining light through a proportionally-scaled pattern in a pre-fabricated mask onto photoresist coated on the die to cause a photoreaction therein. However, in mass production applications, a good yield requires the dies to be rearranged with an accuracy of only 7-10 μm (while the photolithography process is required to provide a positioning accuracy of smaller than 5 μm). This makes it difficult for the photolithography process to achieve a high yield and hence unsuitable for mass production.
There is also a mask-free photolithography technique which utilizes a light modulator in lieu of a mask to create a desired pattern. While this technique can solve the problem of inaccurate rearrangement, as shown in FIG. 3, it requires individual fitting calculations for all the areas to be processed throughout the new carrier 1. Therefore, its throughput in each photolithography cycle is extremely low (each cycle takes 2-3 hours) and cannot catch up with the tact time (5-10 minutes) of the existing FOWLP technique.